diff options
| author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
| commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
| tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/southbridge/intel/fsp_bd82x6x/Makefile.inc | |
| parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) | |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc deleted file mode 100644 index 07192e2a1b..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ /dev/null @@ -1,43 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) - -ramstage-y += pch.c -ramstage-y += azalia.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += me.c -ramstage-y += me_8.x.c -ramstage-y += me_status.c -ramstage-y += watchdog.c - -ramstage-$(CONFIG_ELOG) += elog.c - -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c - -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c - -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c -smm-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-y += early_spi.c - -CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x - -endif |