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authorMartin Roth <martin@coreboot.org>2019-10-23 21:46:03 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-10-30 11:16:56 +0000
commitff744bf0eee875a03dc98dd6792e3ed0ff4456a0 (patch)
tree691260ffe71abac0bb8e2a5607b0d6f1cfb16028 /src/southbridge/intel/common
parent5331a7cff9ebf6f92542eee53e6556a4d5a0dc75 (diff)
src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common')
-rw-r--r--src/southbridge/intel/common/gpio.c6
-rw-r--r--src/southbridge/intel/common/gpio.h2
-rw-r--r--src/southbridge/intel/common/spi.c26
3 files changed, 17 insertions, 17 deletions
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 0245f4fc2d..0669b5fcca 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -124,11 +124,11 @@ int get_gpio(int gpio_num)
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
- unsigned bitmask = 1;
- unsigned vector = 0;
+ unsigned int bitmask = 1;
+ unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 019009ef18..eba2d0130f 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -172,7 +172,7 @@ int get_gpio(int gpio_num);
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 73181cfd54..a84a0dfb8f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -102,7 +102,7 @@ struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
- unsigned databytes;
+ unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@@ -169,7 +169,7 @@ static u8 readb_(const void *addr)
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -178,7 +178,7 @@ static u16 readw_(const void *addr)
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -187,7 +187,7 @@ static u32 readl_(const void *addr)
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -195,21 +195,21 @@ static void writeb_(u8 b, void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, void *addr)
{
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@@ -367,13 +367,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;
@@ -801,8 +801,8 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to read %x-%x which is out of chip\n",
- (unsigned) addr,
- (unsigned) addr+(unsigned) len);
+ (unsigned int) addr,
+ (unsigned int) addr+(unsigned int) len);
return -1;
}
@@ -872,7 +872,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to write 0x%x-0x%x which is out of chip\n",
- (unsigned)addr, (unsigned) (addr+len));
+ (unsigned int)addr, (unsigned int) (addr+len));
return -1;
}
@@ -906,7 +906,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
len -= block_len;
}
printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
- (unsigned) (addr - start), start);
+ (unsigned int) (addr - start), start);
return 0;
}