diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:37:28 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:45 +0000 |
| commit | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (patch) | |
| tree | 042e376cee473f72f143ed76768f50536ab323ef /src/southbridge/intel/common | |
| parent | 298619f6d9adde49b4279c906b0d20a41f919a61 (diff) | |
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/watchdog.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 778a7a9f7f..2eaedab2e8 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -37,13 +37,8 @@ void watchdog_off(void) value = pci_read_config16(dev, PCI_COMMAND); - if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) { - /* Enable I/O space. */ - value |= PCI_COMMAND_IO; - } else { - /* Disable interrupt. */ - value |= PCI_COMMAND_INT_DISABLE; - } + /* Disable interrupt. */ + value |= PCI_COMMAND_INT_DISABLE; pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ |