From c2c634a089fa990418c363e2ff2e5ff70bdd3580 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:37:28 +0100 Subject: nb/sb/cpu: Drop Intel Rangeley support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/southbridge/intel/common/watchdog.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src/southbridge/intel/common') diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 778a7a9f7f..2eaedab2e8 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -37,13 +37,8 @@ void watchdog_off(void) value = pci_read_config16(dev, PCI_COMMAND); - if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) { - /* Enable I/O space. */ - value |= PCI_COMMAND_IO; - } else { - /* Disable interrupt. */ - value |= PCI_COMMAND_INT_DISABLE; - } + /* Disable interrupt. */ + value |= PCI_COMMAND_INT_DISABLE; pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ -- cgit v1.2.3