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authorFrans Hendriks <fhendriks@eltan.com>2019-06-19 11:01:27 +0200
committerMartin Roth <martinroth@google.com>2019-06-20 15:25:51 +0000
commite48be35bca9a0656d1becb0c8a030a11eb8ffaa7 (patch)
tree636b4299c20c7ccc8d0912e672304be6792843af /src/southbridge/intel/common/smbus.h
parentb09de70eda443d2fc9f4891c7647aac4526a8e99 (diff)
southbridge/intel/common/smbus: Add do_i2c_block_write()
Intel Braswell supports i2c block writes using SMBus controller. This support is missing in actual smbus routines. Add do_i2c_block_write() which is a based on do_smbus_block_write() but also write first byte to SMBHSTDAT1. The caller needs to configure the SMBus controller in i2c mode. In i2c mode SMBus controller will send the next sequence: SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT To ensure the the command is send over the bus the SMBHSTCMD register must be written also BUG=N/A TEST=Config eDP for LCD display on Facebook FBG-1701 Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common/smbus.h')
-rw-r--r--src/southbridge/intel/common/smbus.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h
index ded31d0ae2..4875581573 100644
--- a/src/southbridge/intel/common/smbus.h
+++ b/src/southbridge/intel/common/smbus.h
@@ -43,4 +43,6 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device,
/* Only since ICH5 */
int do_i2c_eeprom_read(unsigned int smbus_base, u8 device,
unsigned int offset, unsigned int bytes, u8 *buf);
+int do_i2c_block_write(unsigned int smbus_base, u8 device,
+ unsigned int bytes, u8 *buf);
#endif