From e48be35bca9a0656d1becb0c8a030a11eb8ffaa7 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 19 Jun 2019 11:01:27 +0200 Subject: southbridge/intel/common/smbus: Add do_i2c_block_write() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel Braswell supports i2c block writes using SMBus controller. This support is missing in actual smbus routines. Add do_i2c_block_write() which is a based on do_smbus_block_write() but also write first byte to SMBHSTDAT1. The caller needs to configure the SMBus controller in i2c mode. In i2c mode SMBus controller will send the next sequence: SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT To ensure the the command is send over the bus the SMBHSTCMD register must be written also BUG=N/A TEST=Config eDP for LCD display on Facebook FBG-1701 Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/common/smbus.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/southbridge/intel/common/smbus.h') diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index ded31d0ae2..4875581573 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -43,4 +43,6 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, /* Only since ICH5 */ int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, unsigned int offset, unsigned int bytes, u8 *buf); +int do_i2c_block_write(unsigned int smbus_base, u8 device, + unsigned int bytes, u8 *buf); #endif -- cgit v1.2.3