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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-03 13:05:12 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-06 04:12:13 +0000
commit8d3cc1bcc23a768af879dee160276eae489c5de8 (patch)
tree956049813765cfe6615f7b8359eeca7b23b54a73 /src/southbridge/intel/common/reset.c
parent629ddfd265afed7a5198ddbe58aef66297be4c61 (diff)
soc/intel/tigerlake: Add known GPIO virtual wire information
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/reset.c')
0 files changed, 0 insertions, 0 deletions