diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-07-27 09:49:14 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-28 15:24:13 +0000 |
| commit | 2a7be5bf3061fe8ccd5505f08489ea4671b61f20 (patch) | |
| tree | 4a5bddfb5ed7bdecc8136f4d03e97d577c2f6fcd /src/southbridge/intel/common/gpio.h | |
| parent | 030ba1bff3bbf7210fc16fcd4fdd87f597e5bfa7 (diff) | |
sb/intel/gpio: Cache gpiobase in ramstage and romstage
Implement caching like it's done with pmbase.
Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27664
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/gpio.h')
| -rw-r--r-- | src/southbridge/intel/common/gpio.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 8bd3b961b7..97b7783400 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -19,11 +19,6 @@ #include <stdint.h> #include <compiler.h> -/* LPC GPIO Base Address Register */ -#define GPIO_BASE 0x48 -/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) - /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04 |