From 2a7be5bf3061fe8ccd5505f08489ea4671b61f20 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 27 Jul 2018 09:49:14 +0200
Subject: sb/intel/gpio: Cache gpiobase in ramstage and romstage

Implement caching like it's done with pmbase.

Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27664
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/common/gpio.h | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'src/southbridge/intel/common/gpio.h')

diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 8bd3b961b7..97b7783400 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -19,11 +19,6 @@
 #include <stdint.h>
 #include <compiler.h>
 
-/* LPC GPIO Base Address Register */
-#define GPIO_BASE		0x48
-/* PCI Configuration Space (D31:F0): LPC */
-#define PCH_LPC_DEV		PCI_DEV(0, 0x1f, 0)
-
 /* ICH7 GPIOBASE */
 #define GPIO_USE_SEL	0x00
 #define GP_IO_SEL	0x04
-- 
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