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authorAngel Pons <th3fanbus@gmail.com>2020-06-01 19:31:53 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-21 18:22:52 +0000
commit90e9f5472680bbc44fe4e23b390a9323f8c59643 (patch)
treeada8a2e33d2cb3a125f6e86d807d443409e814d7 /src/southbridge/intel/common/early_smbus.h
parent492d801aabeecf2dbf0787784bbb97ab2a901dcc (diff)
ironlake/ibexpeak: Move early_smbus.c to common code
We will update the other platforms to use this common code in susbsequent commits. While we are at it, reflow a broken line, define the SMBus PCI device in the header and fix whitespace. Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/early_smbus.h')
-rw-r--r--src/southbridge/intel/common/early_smbus.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h
new file mode 100644
index 0000000000..d6a7cbbcce
--- /dev/null
+++ b/src/southbridge/intel/common/early_smbus.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H
+#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H
+
+#include <device/pci_def.h>
+
+#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3)
+
+#define SMB_BASE PCI_BASE_ADDRESS_4
+#define HOSTC 0x40
+
+/* HOSTC bits */
+#define I2C_EN (1 << 2)
+#define SMB_SMI_EN (1 << 1)
+#define HST_EN (1 << 0)
+
+#endif /* SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H */