From 90e9f5472680bbc44fe4e23b390a9323f8c59643 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 1 Jun 2020 19:31:53 +0200 Subject: ironlake/ibexpeak: Move early_smbus.c to common code We will update the other platforms to use this common code in susbsequent commits. While we are at it, reflow a broken line, define the SMBus PCI device in the header and fix whitespace. Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/southbridge/intel/common/early_smbus.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 src/southbridge/intel/common/early_smbus.h (limited to 'src/southbridge/intel/common/early_smbus.h') diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h new file mode 100644 index 0000000000..d6a7cbbcce --- /dev/null +++ b/src/southbridge/intel/common/early_smbus.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H + +#include + +#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3) + +#define SMB_BASE PCI_BASE_ADDRESS_4 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +#endif /* SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H */ -- cgit v1.2.3