diff options
author | Lin Huang <hl@rock-chips.com> | 2016-09-21 18:19:24 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-07 17:54:37 +0200 |
commit | e757bf9acd287b3452947001d8b7550bd72ed0dd (patch) | |
tree | adca0a8559e81d5b65176c8f04092c0b23ff50f4 /src/southbridge/intel/bd82x6x | |
parent | e865a3d89bf1a64f0bd1ecf37f6dec6f3d5ae333 (diff) |
rockchip/rk3399: Improve dram stability when run at high frequency
There are two modifications in the driver:
1. Correctly set speeds based on DDR frequency.
Control the speeds in the predriver circuits to reduce power.
SPEED[1:0]
2'b00:less than 800Mbps(400MHz)
2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz)
2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz)
2b11 : 3200Mbps and greater
2. Configure the number of cycles for the phy clock pll wait time after
locking, based on the DDR config file.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2
Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/387428
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16722
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
0 files changed, 0 insertions, 0 deletions