summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x
diff options
context:
space:
mode:
authorNico Huber <nico.huber@secunet.com>2019-02-28 12:43:21 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-04-15 20:59:48 +0000
commit56473ca9a7ca96e862897192b2a7dba4f162aa86 (patch)
treedef97400fff9572266c9619c4651541def50c995 /src/southbridge/intel/bd82x6x
parent14929253a52cebaedbbe918972ea12568e29dfd9 (diff)
sb/intel/bd82x6x/sata: Clean up IDE modes
Don't set legacy timing values that don't affect the hardware but enable the OOB retry mode as already done on the AHCI path. Change-Id: I0b078d7790ca801a89066ef6a161d900be5eb778 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c22
1 files changed, 5 insertions, 17 deletions
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 6c6e5be598..75a1b1a363 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -187,26 +187,14 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n");
}
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_SITRE | IDE_ISP_3_CLOCKS |
- IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
+ /* Enable I/O decoding */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
- /* Port enable */
+ /* Port enable + OOB retry mode */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f;
- reg16 |= config->sata_port_map;
+ reg16 |= config->sata_port_map | 0x8000;
pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */