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authorVladimir Serbinenko <phcoder@gmail.com>2014-10-28 23:43:20 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-11-19 21:09:51 +0100
commit36fa5b80843d836518eb89f46747e80ed6b5d96f (patch)
treea36f498a48aaa8764df768ff3616ff476f62a07b /src/southbridge/intel/bd82x6x
parent10dd0e3171bc631fd5d83d4f42aa376edd3c6d55 (diff)
i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug
This implementation is more compact, unified and works with windows as well. Tested under windows and under Debian GNU/Linux. Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7296 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc1
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pcie.asl21
-rw-r--r--src/southbridge/intel/bd82x6x/chip.h2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c10
-rw-r--r--src/southbridge/intel/bd82x6x/pcie.c15
5 files changed, 28 insertions, 21 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 3d33edcd13..621a74341c 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-y += usb_xhci.c
ramstage-y += me.c
ramstage-y += me_8.x.c
ramstage-y += smbus.c
+ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
index 14ae449e7e..934cf782e9 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
@@ -155,16 +155,6 @@ Device (RP03)
{
Return (IRQM (RPPN))
}
-#ifdef RP03_IS_EXPRESSCARD
- Device (SLOT)
- {
- Name (_ADR, 0x00)
- Method (_RMV, 0, NotSerialized)
- {
- Return (0x01)
- }
- }
-#endif
}
Device (RP04)
@@ -177,17 +167,6 @@ Device (RP04)
{
Return (IRQM (RPPN))
}
-
-#ifdef RP04_IS_EXPRESSCARD
- Device (SLOT)
- {
- Name (_ADR, 0x00)
- Method (_RMV, 0, NotSerialized)
- {
- Return (0x01)
- }
- }
-#endif
}
Device (RP05)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index e5da531e75..d4adfd5c9f 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -100,6 +100,8 @@ struct southbridge_intel_bd82x6x_config {
int p_cnt_throttling_supported;
int c2_latency;
int docking_supported;
+
+ uint8_t pcie_hotplug_map[8];
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 80d6284629..3c559462ee 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -38,6 +38,7 @@
#include <cpu/x86/smm.h>
#include "pch.h"
#include "nvs.h"
+#include <southbridge/intel/common/pciehp.h>
#define NMI_OFF 0
@@ -838,6 +839,14 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.addrh = 0x0;
}
+static void southbridge_fill_ssdt(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ config_t *chip = dev->chip_info;
+
+ intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+}
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -848,6 +857,7 @@ static struct device_operations device_ops = {
.enable_resources = pch_lpc_enable_resources,
.write_acpi_tables = acpi_write_hpet,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .acpi_fill_ssdt_generator = southbridge_fill_ssdt,
.init = lpc_init,
.enable = pch_lpc_enable,
.scan_bus = scan_static_bus,
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index fadb43ff2b..4769dd53d0 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
+#include <southbridge/intel/common/pciehp.h>
#include "pch.h"
static void pch_pcie_pm_early(struct device *dev)
@@ -218,6 +219,7 @@ static void pci_init(struct device *dev)
{
u16 reg16;
u32 reg32;
+ struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
@@ -255,6 +257,14 @@ static void pci_init(struct device *dev)
reg16 = pci_read_config16(dev, 0x1e);
//reg16 |= 0xf900;
pci_write_config16(dev, 0x1e, reg16);
+
+ /* Enable expresscard hotplug events. */
+ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+ pci_write_config32(dev, 0xd8,
+ pci_read_config32(dev, 0xd8)
+ | (1 << 30));
+ pci_write_config16(dev, 0x42, 0x142);
+ }
}
static void pch_pcie_enable(device_t dev)
@@ -266,10 +276,15 @@ static void pch_pcie_enable(device_t dev)
static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
{
unsigned int ret;
+ struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
/* Normal PCIe Scan */
ret = pciexp_scan_bridge(dev, max);
+ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+ intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
+ }
+
/* Late Power Management init after bridge device enumeration */
pch_pcie_pm_late(dev);