diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-08-28 14:32:05 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-08-29 20:24:18 +0000 |
| commit | eeab2710efbfc4393756ae89478f649f035b3732 (patch) | |
| tree | 89f3a522a2dec780776967fe7f7730aada29a6b3 /src/southbridge/intel/bd82x6x/reset.c | |
| parent | feefbd71270123a4071395acc32878bf6bb10ae2 (diff) | |
mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time)
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.
BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.
I2C0: 393 - 397
I2C1: 393 - 400
I2C2: 392 - 400
I2C4: 392 - 400
I2C5: 392 - 400
Change-Id: I3e12c75eb7e82a83aa6a6bcfcc11c12f83f2d3d4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/reset.c')
0 files changed, 0 insertions, 0 deletions