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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-03 17:00:28 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-07 19:34:23 +0000 |
| commit | 66d090b66446863151790cb0bbbe604d74508846 (patch) | |
| tree | 4f9938bedc6804297cadbc418a8a346e18cc54dc /src/southbridge/intel/bd82x6x/pcie.c | |
| parent | f85e3cd269010de4114ac9b8eaabf60555e20ea5 (diff) | |
mb/google/brya/acpi: Fix PERST# handling in GC6 exit
PERST# is supposed to be de-asserted in GC6 exit, but the original
patch used the CTXS Method, which drives a GPIO low, instead of
STXS, because PERST# is active-low. This patch fixes that.
BUG=b:214581763
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pcie.c')
0 files changed, 0 insertions, 0 deletions