diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2017-02-21 12:52:34 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-14 17:13:56 +0200 |
| commit | b31a066e0d0c08939f41c12a8c3721d56b78b43c (patch) | |
| tree | 31cc504661f56f2f23bf44b178259f0e4a4958b9 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 3eec9dda1fa7aed3cd6a47232201c23303b3d686 (diff) | |
northbridge/via/cn700: Add some delays during raminit
Otherwise, it locks up quickly. Not sure which ones are actually needed
and why, couldn't bisect it into removing even a single one.
The factory BIOS on a Neoware G170 does 200 0xed reads between setting
the registers too.
Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18893
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
0 files changed, 0 insertions, 0 deletions