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author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 17:47:22 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-05 15:06:03 +0000 |
commit | 372dfe0e20f7e56ba2acf872392da41f5ee28633 (patch) | |
tree | d67a9d94b29ac12c03da6946939cdae45e7c3b42 /src/southbridge/intel/bd82x6x/me_8.x.c | |
parent | 1a066312437fc2f8ac8bfad0dcfeb08e46c931ec (diff) |
sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
Since the LPC bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the LPC bridge device operations to the PCI
device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me_8.x.c')
0 files changed, 0 insertions, 0 deletions