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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:40:21 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-21 16:29:35 +0000
commit131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef (patch)
treeaccfc86126dba3bf22fe731689ee791894a3bcaa /src/southbridge/intel/bd82x6x/lpc.c
parentb69bbfe1ef52421f0bbe1e632d99dc264660ee02 (diff)
src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 2407d92dc1..df5625afa5 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -734,7 +734,6 @@ static struct device_operations device_ops = {
.ops_pci = &pci_dev_ops_pci,
};
-
/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
* Intel C200 Series Chipset
*/