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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-08 14:30:06 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 04:22:57 +0100 |
| commit | 924342bb2b9e429d66a693503c9f944655da4bb8 (patch) | |
| tree | 835cf560582f2bf316acd490072cb04f1c68dfb6 /src/southbridge/intel/bd82x6x/gpio.c | |
| parent | fb8632ab58de871ef3a25b5e57c7a2e95f04a0d8 (diff) | |
SPI: Add Fast Read to the OPMENU for locked down SPI
The chips we are using do not use BE52 (block erase 0x52)
so we can use that opcode menu location to enable fast read.
Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/gpio.c')
0 files changed, 0 insertions, 0 deletions