sb/intel/common: Create a common PCH finalise implementation

The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.

Lynx Point now benefits from being able to write-protect the flash chip.

For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.

Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.

Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.

Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 0 insertions, 76 deletions

diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
deleted file mode 100644
index a08535e979..0000000000
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <console/post_codes.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/common/pmbase.h>
-#include <spi-generic.h>
-#include "chip.h"
-#include "pch.h"
-
-void intel_pch_finalize_smm(void)
-{
-	if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) ||
-	    IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) {
-		/* Copy flash regions from FREG0-4 to PR0-4
-		   and enable write protection bit31 */
-		int i;
-		u32 lockmask = (1 << 31);
-		if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS))
-			lockmask |= (1 << 15);
-		for (i = 0; i < 20; i += 4)
-			RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask;
-	}
-
-	/* Lock SPIBAR */
-	RCBA32_OR(0x3804, (1 << 15));
-
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
-	/* Re-init SPI driver to handle locked BAR */
-	spi_init();
-#endif
-
-	/* TCLOCKDN: TC Lockdown */
-	RCBA32_OR(0x0050, (1 << 31));
-
-	/* BIOS Interface Lockdown */
-	RCBA32_OR(0x3410, (1 << 0));
-
-	/* Function Disable SUS Well Lockdown */
-	RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
-
-	/* Global SMI Lock */
-	pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4);
-
-	/* GEN_PMCON Lock */
-	pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
-
-	/* ETR3: CF9GR Lockdown */
-	pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
-
-	/* R/WO registers */
-	RCBA32(0x21a4) = RCBA32(0x21a4);
-	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
-		    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
-
-	/* TCO_Lock */
-	write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
-
-	/* Indicate finalize step with post code */
-	outb(POST_OS_BOOT, 0x80);
-}