summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x/early_thermal.c
diff options
context:
space:
mode:
authorDivagar Mohandass <divagar.mohandass@intel.com>2015-10-05 16:21:14 +0530
committerMartin Roth <martinroth@google.com>2016-01-28 00:03:12 +0100
commit2abcffcc4014a3a5344d01d76c50d707eae62d17 (patch)
tree201fd07e213bc23b51af66c2a57f06f4cb0d859b /src/southbridge/intel/bd82x6x/early_thermal.c
parent39f84fa6623f8981816682138d02acf3c31f3672 (diff)
intel/strago: EC_IN_RW gpio input configuration.
Configure EC_IN_RW signal as gpio input. TEST=Boot to Chrome OS in normal mode and enter recovery mode use ctrl-d to switch to Dev mode. Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304040 Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/13124 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_thermal.c')
0 files changed, 0 insertions, 0 deletions