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| author | Evgeny Zinoviev <me@ch1p.io> | 2021-02-07 01:49:30 +0300 |
|---|---|---|
| committer | Evgeny Zinoviev <me@ch1p.io> | 2021-02-07 01:49:30 +0300 |
| commit | ee835aed102f4651f30234eda1110fa106575fdd (patch) | |
| tree | e3368029dfe7b14b77892b6f48dbd0d11614057a /src/southbridge/intel/bd82x6x/early_me_mrc.c | |
| parent | 8f96216188ae440be6af63af650e26f05a86fd81 (diff) | |
| parent | b01b13866a6049ac81bd11861a29c3f4e591f951 (diff) | |
Merge branch 'me-disable' into mbp101_medisable_1
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_me_mrc.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me_mrc.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 0b11fd0e81..180e466bd4 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -6,6 +6,7 @@ #include <delay.h> #include <device/pci_def.h> #include <halt.h> +#include <southbridge/intel/common/me.h> #include <string.h> #include "me.h" #include "pch.h" @@ -96,22 +97,6 @@ int intel_early_me_uma_size(void) return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset; |