From dc413403cfebf233d9cd03fa629744fc4fc1b563 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 6 Feb 2021 23:22:33 +0100 Subject: sb/intel: Extract `set_global_reset` function To avoid duplicating this function in ramstage, factor it out. Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Signed-off-by: Angel Pons --- src/southbridge/intel/bd82x6x/early_me_mrc.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/early_me_mrc.c') diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 0b11fd0e81..180e466bd4 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include "me.h" #include "pch.h" @@ -96,22 +97,6 @@ int intel_early_me_uma_size(void) return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset; -- cgit v1.2.3