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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-08-20 16:50:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-15 07:49:54 +0000 |
| commit | b50b6a5fa7e3d1810ab60dcc9b646ab7914b79e3 (patch) | |
| tree | 33f3b41e29717dcf8068b231c09d8f8b33173dd5 /src/southbridge/intel/bd82x6x/azalia.c | |
| parent | ed8d777cecf7162a688b4683a4d39333999dcfc7 (diff) | |
nb/intel/sandybridge: Add x86_64 support
Fix compilation on x86_64 by using compatible types.
The MRC blob isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200:
* Still boots on x86_32.
* Boots to payload in x86_64
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/azalia.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/azalia.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index dcb0bb40f0..1f14c422a8 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -165,7 +165,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); |