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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 08:24:12 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:50:17 +0100 |
| commit | cc37bbd7acaaa060fa272115aa077baabac402c4 (patch) | |
| tree | 395673beb5f98389572bd0e4423189e03dc19dcd /src/southbridge/amd | |
| parent | b995f436b355ec357788d3a8c11c70bf5ec437df (diff) | |
AMD binaryPI: Use explicit PCI IO config access in bootblock
This allows us to set MMCONF_SUPPORT_DEFAULT since we enable
MMCONF early in romstage.
Change-Id: I380cf483bfe4e2d64969110ae6d5d04c3ced2418
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17532
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/bootblock.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ff5219920d..32b129862d 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -34,15 +34,15 @@ static void hudson_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -52,9 +52,9 @@ static void hudson_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void) |