CBMEM: Backup top_of_ram instead of cbmem_toc

AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.

TODO: Redesign these get_top_of_ram() functions from scratch.

Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

7 files changed, 32 insertions, 21 deletions

diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a0319abdf9..96861c99ca 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void)
 }
 #endif
 
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
 {
 	uint32_t xdata = 0;
 	int xnvram_pos = 0xf8, xi;
@@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void)
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
 		xnvram_pos++;
 	}
-	return (struct cbmem_entry *) xdata;
+	return (unsigned long) xdata;
 }
 
 #endif
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index e4cbc07342..21399117f3 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,9 +40,9 @@ int acpi_get_sleep_type(void)
 }
 #endif
 
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
 {
-	u32 dword = (u32) toc;
+	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xf8, i; /* temp */
 	/* printk(BIOS_DEBUG, "dword=%x\n", dword); */
 	for (i = 0; i<4; i++) {
@@ -132,19 +132,22 @@ void hudson_enable(device_t dev)
 	}
 }
 
-struct cbmem_entry *get_cbmem_toc(void)
+#if CONFIG_HAVE_ACPI_RESUME
+unsigned long get_top_of_ram(void)
 {
 	uint32_t xdata = 0;
 	int xnvram_pos = 0xf8, xi;
+	if (acpi_get_sleep_type() != 3)
+		return 0;
 	for (xi = 0; xi<4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
 		xnvram_pos++;
 	}
-	return (struct cbmem_entry *) xdata;
+	return (unsigned long) xdata;
 }
-
+#endif
 
 struct chip_operations southbridge_amd_agesa_hudson_ops = {
 	CHIP_NAME("ATI HUDSON")
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index 826ac057c4..91d7d2fd51 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -27,9 +27,9 @@
 #define BIOSRAM_INDEX   0xcd4
 #define BIOSRAM_DATA    0xcd5
 
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
 {
-	u32 dword = (u32) toc;
+	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xfc, i;
 	for (i = 0; i<4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 90ad5a9f62..852054883e 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -37,9 +37,9 @@ int acpi_get_sleep_type(void)
 #endif
 
 #ifndef __PRE_RAM__
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
 {
-	u32 dword = (u32) toc;
+	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xf8, i; /* temp */
 	printk(BIOS_DEBUG, "dword=%x\n", dword);
 	for (i = 0; i<4; i++) {
@@ -51,18 +51,22 @@ void set_cbmem_toc(struct cbmem_entry *toc)
 }
 #endif
 
-struct cbmem_entry *get_cbmem_toc(void)
+#if CONFIG_HAVE_ACPI_RESUME
+unsigned long get_top_of_ram(void)
 {
 	u32 xdata = 0;
 	int xnvram_pos = 0xf8, xi;
+	if (acpi_get_sleep_type() != 3)
+		return 0;
 	for (xi = 0; xi<4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
 		xnvram_pos++;
 	}
-	return (struct cbmem_entry *) xdata;
+	return (unsigned long) xdata;
 }
+#endif
 
 /**
  * @brief South Bridge CIMx configuration
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index a16fc9f2b2..ddba1a8438 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -729,19 +729,21 @@ int acpi_is_wakeup_early(void)
 	printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
 	return (((tmp & (7 << 10)) >> 10) == 3);
 }
-#endif
 
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
 {
 	uint32_t xdata = 0;
 	int xnvram_pos = 0xfc, xi;
+	if (!acpi_is_wakeup_early())
+		return 0;
 	for (xi = 0; xi<4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
 		xnvram_pos++;
 	}
-	return (struct cbmem_entry *) xdata;
+	return (unsigned long) xdata;
 }
+#endif
 
 #endif
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 23775b0cf2..a175210be6 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -84,9 +84,9 @@ static void lpc_init(device_t dev)
 	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
 }
 
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
 {
-	u32 dword = (u32) toc;
+	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xfc, i;
 	for (i = 0; i<4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 4f0c98ae13..b3d16bf173 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -673,19 +673,21 @@ static int acpi_is_wakeup_early(void)
 	printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
 	return (((tmp & (7 << 10)) >> 10) == 3);
 }
-#endif
 
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
 {
 	uint32_t xdata = 0;
 	int xnvram_pos = 0xfc, xi;
+	if (!acpi_is_wakeup_early())
+		return 0;
 	for (xi = 0; xi<4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
 		xnvram_pos++;
 	}
-	return (struct cbmem_entry *) xdata;
+	return (unsigned long) xdata;
 }
+#endif
 
 #endif