sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN()

Change-Id: I731fd4ecfab679cd3d830a89bc82c56cf9008bc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

3 files changed, 48 insertions, 48 deletions

diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 25e087f641..e5366e97fc 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -347,11 +347,11 @@ static void sb900_enable(struct device *dev)
 //-	commonInitEarlyPost(sb_config);
 
 	switch (dev->path.pci.devfn) {
-	case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */
+	case PCI_DEVFN(0x10, 0): /* XHCI-USB */
 //-		usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
 		break;
 
-	case (0x11 << 3) | 0: /* 0:11.0  SATA */
+	case PCI_DEVFN(0x11, 0): /* SATA */
 		if (dev->enabled) {
 			sb_config->SATAMODE.SataMode.SataController = ENABLED;
 			if (sb_chip->boot_switch_sata_ide == 1)
@@ -365,18 +365,18 @@ static void sb900_enable(struct device *dev)
 //-		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 		break;
 
-	case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
-	case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
-	case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
-	case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
-	case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+	case PCI_DEVFN(0x12, 0): /* OHCI-USB1 */
+	case PCI_DEVFN(0x12, 2): /* EHCI-USB1 */
+	case PCI_DEVFN(0x13, 0): /* OHCI-USB2 */
+	case PCI_DEVFN(0x13, 2): /* EHCI-USB2 */
+	case PCI_DEVFN(0x14, 5): /* OHCI-USB4 */
 //-		usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
 		break;
 
-	case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+	case PCI_DEVFN(0x14, 0): /* SMBUS */
 		break;
 
-	case (0x14 << 3) | 1: /* 0:14:1 IDE */
+	case PCI_DEVFN(0x14, 1): /* IDE */
 		if (dev->enabled) {
 			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
 		} else {
@@ -385,7 +385,7 @@ static void sb900_enable(struct device *dev)
 //-		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 		break;
 
-	case (0x14 << 3) | 2: /* 0:14:2 HDA */
+	case PCI_DEVFN(0x14, 2): /* HDA */
 		if (dev->enabled) {
 			if (sb_config->AzaliaController == AZALIA_DISABLE) {
 				sb_config->AzaliaController = AZALIA_AUTO;
@@ -399,13 +399,13 @@ static void sb900_enable(struct device *dev)
 		break;
 
 
-	case (0x14 << 3) | 3: /* 0:14:3 LPC */
+	case PCI_DEVFN(0x14, 3): /* LPC */
 		break;
 
-	case (0x14 << 3) | 4: /* 0:14:4 PCI */
+	case PCI_DEVFN(0x14, 4): /* PCI */
 		break;
 
-	case (0x14 << 3) | 6: /* 0:14:6 GEC */
+	case PCI_DEVFN(0x14, 6): /* GEC */
 		if (dev->enabled) {
 			sb_config->GecConfig = 0;
 			printk(BIOS_DEBUG, "gec enabled\n");
@@ -416,10 +416,10 @@ static void sb900_enable(struct device *dev)
 //-		gecInitBeforePciEnum(sb_config); // Init GEC
 		break;
 
-	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
-	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
-	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
-	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
+	case PCI_DEVFN(0x15, 0): /* PCIe PortA */
+	case PCI_DEVFN(0x15, 1): /* PCIe PortB */
+	case PCI_DEVFN(0x15, 2): /* PCIe PortC */
+	case PCI_DEVFN(0x15, 3): /* PCIe PortD */
 		gpp_port = (dev->path.pci.devfn) & 0x03;
 		if (dev->enabled) {
 			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index b7ff58d90c..8929f3fdfc 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -167,53 +167,53 @@ void sb7xx_51xx_enable(struct device *dev)
 		return;
 
 	switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
-	case (0x11 << 3) | 0:
+	case PCI_DEVFN(0x11, 0):
 		index = 8;
 		set_sm_enable_bits(sm_dev, 0xac, 1 << index,
 				   (dev->enabled ? 1 : 0) << index);
 		index += 32 * 3;
 		break;
-	case (0x12 << 3) | 0:
-	case (0x12 << 3) | 1:
-	case (0x12 << 3) | 2:
+	case PCI_DEVFN(0x12, 0):
+	case PCI_DEVFN(0x12, 1):
+	case PCI_DEVFN(0x12, 2):
 		index = dev->path.pci.devfn & 3;
 		set_sm_enable_bits(sm_dev, 0x68, 1 << index,
 				   (dev->enabled ? 1 : 0) << index);
 		index += 32 * 2;
 		break;
-	case (0x13 << 3) | 0:
-	case (0x13 << 3) | 1:
-	case (0x13 << 3) | 2:
+	case PCI_DEVFN(0x13, 0):
+	case PCI_DEVFN(0x13, 1):
+	case PCI_DEVFN(0x13, 2):
 		index = (dev->path.pci.devfn & 3) + 4;
 		set_sm_enable_bits(sm_dev, 0x68, 1 << index,
 				   (dev->enabled ? 1 : 0) << index);
 		index += 32 * 2;
 		break;
-	case (0x14 << 3) | 5:
+	case PCI_DEVFN(0x14, 5):
 		index = 7;
 		set_sm_enable_bits(sm_dev, 0x68, 1 << index,
 				   (dev->enabled ? 1 : 0) << index);
 		index += 32 * 2;
 		break;
-	case (0x14 << 3) | 0:
+	case PCI_DEVFN(0x14, 0):
 		index = 0;
 		break;
-	case (0x14 << 3) | 1:
+	case PCI_DEVFN(0x14, 1):
 		index = 1;
 		break;
-	case (0x14 << 3) | 2:
+	case PCI_DEVFN(0x14, 2):
 		index = 3;
 		set_pmio_enable_bits(sm_dev, 0x59, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);
 		index += 32 * 4;
 		break;
-	case (0x14 << 3) | 3:
+	case PCI_DEVFN(0x14, 3):
 		index = 20;
 		set_sm_enable_bits(sm_dev, 0x64, 1 << index,
 				   (dev->enabled ? 1 : 0) << index);
 		index += 32 * 1;
 		break;
-	case (0x14 << 3) | 4:
+	case PCI_DEVFN(0x14, 4):
 		index = 4;
 		break;
 	default:
diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c
index bd4dc68ca2..eda4d304d3 100644
--- a/src/southbridge/amd/sb800/sb800.c
+++ b/src/southbridge/amd/sb800/sb800.c
@@ -294,7 +294,7 @@ void sb800_enable(struct device *dev)
 	printk(BIOS_DEBUG, "sb800_enable() 2\n");
 
 	switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
-	case (0x11 << 3) | 0:
+	case PCI_DEVFN(0x11, 0):
 		index = 8;
 		set_pmio_enable_bits(0xDA, 1 << 0,
 				     (dev->enabled ? 1 : 0) << 0);
@@ -307,63 +307,63 @@ void sb800_enable(struct device *dev)
 		pci_write_config32(dev, 0x40, dword);//for (;;);
 		index += 32 * 3;
 		break;
-	case (0x12 << 3) | 0:
-	case (0x12 << 3) | 2:
+	case PCI_DEVFN(0x12, 0):
+	case PCI_DEVFN(0x12, 2):
 		index = (dev->path.pci.devfn & 0x3) / 2;
 		set_pmio_enable_bits(0xEF, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);
 		break;
-	case (0x13 << 3) | 0:
-	case (0x13 << 3) | 2:
+	case PCI_DEVFN(0x13, 0):
+	case PCI_DEVFN(0x13, 2):
 		index = (dev->path.pci.devfn & 0x3) / 2 + 2;
 		set_pmio_enable_bits(0xEF, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);
 		index += 32 * 2;
 		break;
-	case (0x14 << 3) | 0:
+	case PCI_DEVFN(0x14, 0):
 		index = 0;
 		break;
-	case (0x14 << 3) | 1:
+	case PCI_DEVFN(0x14, 1):
 		index = 1;
 		set_pmio_enable_bits(0xDA, 1 << 3,
 				     (dev->enabled ? 0 : 1) << 3);
 		break;
-	case (0x14 << 3) | 2:
+	case PCI_DEVFN(0x14, 2):
 		index = 0;
 		set_pmio_enable_bits(0xEB, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);
 		break;
-	case (0x14 << 3) | 3:
+	case PCI_DEVFN(0x14, 3):
 		index = 0;
 		set_pmio_enable_bits(0xEC, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);
 		index += 32 * 1;
 		break;
-	case (0x14 << 3) | 4:
+	case PCI_DEVFN(0x14, 4):
 		index = 0;
 		set_pmio_enable_bits(0xEA, 1 << index,
 				     (dev->enabled ? 0 : 1) << index);
 		break;
-	case (0x14 << 3) | 5:
+	case PCI_DEVFN(0x14, 5):
 		index = 6;
 		set_pmio_enable_bits(0xEF, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);
 		break;
-	case (0x14 << 3) | 6:
+	case PCI_DEVFN(0x14, 6):
 		index = 0;
 		set_pmio_enable_bits(0xF6, 1 << index,
 				     (dev->enabled ? 0 : 1) << index);
 		break;
-	case (0x15 << 3) | 0:
+	case PCI_DEVFN(0x15, 0):
 		set_sb800_gpp(dev);
 		index = 4;
 		break;
-	case (0x15 << 3) | 1:
-	case (0x15 << 3) | 2:
-	case (0x15 << 3) | 3:
+	case PCI_DEVFN(0x15, 1):
+	case PCI_DEVFN(0x15, 2):
+	case PCI_DEVFN(0x15, 3):
 		break;
-	case (0x16 << 3) | 0:
-	case (0x16 << 3) | 2:
+	case PCI_DEVFN(0x16, 0):
+	case PCI_DEVFN(0x16, 2):
 		index = (dev->path.pci.devfn & 0x3) / 2 + 4;
 		set_pmio_enable_bits(0xEF, 1 << index,
 				     (dev->enabled ? 1 : 0) << index);