reset: Finalize move to new API

Move soft_reset() to `southbridge/amd/common/` it's only used for
amdfam10 now.

Drop hard_reset() for good.

Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 39 insertions, 1 deletions

diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index d04646cf85..ce29bf1e77 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -15,6 +15,7 @@
 
 #include "amd8111.h"
 #include <reset.h>
+#include <southbridge/amd/common/reset.h>
 
 unsigned get_sbdn(unsigned bus)
 {
diff --git a/src/southbridge/amd/common/reset.h b/src/southbridge/amd/common/reset.h
new file mode 100644
index 0000000000..ce101cb2dc
--- /dev/null
+++ b/src/southbridge/amd/common/reset.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _AMD_SB_RESET_H_
+#define _AMD_SB_RESET_H_
+
+#include <arch/cache.h>
+#include <console/console.h>
+#include <halt.h>
+
+/* Implement the bare reset, e.g. write to cf9. */
+void do_soft_reset(void);
+
+/* Prepare for reset, run do_soft_reset(), halt. */
+static inline __noreturn void soft_reset(void)
+{
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	dcache_clean_all();
+	do_soft_reset();
+	halt();
+}
+
+#endif	/* _AMD_SB_RESET_H_ */
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index f5f7a2c2f3..4c9b0f4056 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -18,6 +18,7 @@
 
 #include <arch/io.h>
 #include <reset.h>
+#include <southbridge/amd/common/reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 2ace9926c7..6835d993c4 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -19,6 +19,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/common/reset.h>
 #include "sb800.h"
 #include "smbus.c"
 
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 543cb0efbf..8b6f22a793 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -22,7 +22,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
 #include <option.h>
-#include <reset.h>
+#include <southbridge/amd/common/reset.h>
 #include "sr5650.h"
 #include "cmn.h"