diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-23 19:18:02 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-26 19:34:20 +0000 |
| commit | 3136424e48b533a29258d5b2412439db066ff744 (patch) | |
| tree | 62866c609208c8418500d47448698a7179a8106a /src/southbridge/amd | |
| parent | ee3d09b48ed572df059de50537e6ba0e4afbfbf1 (diff) | |
soc/amd/common/block/acpimmio: add Kconfig option for biosram accessors
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/Kconfig | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 0616277545..cf5b21c319 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index ecfc1e1c5f..a151bae370 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -10,6 +10,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_PCI_MMCONF if SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index ff1f5d9c23..fa60d17654 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |