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authorDavid Hendricks <dhendrix@chromium.org>2013-04-18 16:45:47 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-04-19 18:24:14 +0200
commitec10ce8971221463314bf1f88e054e1d399bd7a9 (patch)
tree9c054182353c19ad2ed801d49ccffdec209232c4 /src/southbridge/amd/sr5650/cmn.h
parent954d25484b0f4d4881c1b6d5662c587c85c920a2 (diff)
google/snow: Minor clean-ups for display setup code in ramstage
This just cleans up a few areas: - Removed an unnecessary delay from exynos_dp_bridge_setup() - The delay at the end of exynos_dp_bridge_init() is necessary, so removed the comment suggesting that it might not be. - Simplified exynos_dp_hotplug Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/amd/sr5650/cmn.h')
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