diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-21 12:06:54 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-23 15:45:33 +0200 |
| commit | 7f9df96825100059e3ee1bc78f8b7154441b2751 (patch) | |
| tree | 7927ecdbff84593256b829bcbe5d4d191bb687ab /src/southbridge/amd/rs780 | |
| parent | d6e96864c9245b82222dada6fea2b89ccb7fecfd (diff) | |
src/southbridge: Remove unnecessary whitespace before "\n" and "\t"
Change-Id: I42cc5b8736e73728c5deec6349e8d2a814e19e83
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16281
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Omar Pakker
Diffstat (limited to 'src/southbridge/amd/rs780')
| -rw-r--r-- | src/southbridge/amd/rs780/gfx.c | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 8499a4d599..6d27d56491 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -197,7 +197,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { tempdev = dev_find_slot(Bus, Dev << 3); Value = pci_read_config32(tempdev, 0); - printk(BIOS_DEBUG, "Dev ID %x \n", Value); + printk(BIOS_DEBUG, "Dev ID %x\n", Value); if((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB @@ -228,7 +228,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) } } } - printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); + printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x\n", MMIOStart, MMIOLimit); if (MMIOStart < MMIOLimit) { Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO); @@ -570,44 +570,44 @@ static void internal_gfx_pci_dev_init(struct device *dev) poweron_ddi_lanes(nb_dev); printk(BIOS_DEBUG,"vgainfo:\n" - " ulBootUpEngineClock:%lu \n" - " ulBootUpUMAClock:%lu \n" - " ulBootUpSidePortClock:%lu \n" - " ulMinSidePortClock:%lu \n" - " ulSystemConfig:%lu \n" - " ulBootUpReqDisplayVector:%lu \n" - " ulOtherDisplayMisc:%lu \n" - " ulDDISlot1Config:%lu \n" - " ulDDISlot2Config:%lu \n" - - " ucMemoryType:%u \n" - " ucUMAChannelNumber:%u \n" - " ucDockingPinBit:%u \n" - " ucDockingPinPolarity:%u \n" - - " ulDockingPinCFGInfo:%lu \n" - " ulCPUCapInfo: %lu \n" - - " usNumberOfCyclesInPeriod:%hu \n" - " usMaxNBVoltage:%hu \n" - " usMinNBVoltage:%hu \n" - " usBootUpNBVoltage:%hu \n" - - " ulHTLinkFreq:%lu \n" - - " usMinHTLinkWidth:%hu \n" - " usMaxHTLinkWidth:%hu \n" - " usUMASyncStartDelay:%hu \n" - " usUMADataReturnTime:%hu \n" - " usLinkStatusZeroTime:%hu \n" - - " ulHighVoltageHTLinkFreq:%lu \n" - " ulLowVoltageHTLinkFreq:%lu \n" - - " usMaxUpStreamHTLinkWidth:%hu \n" - " usMaxDownStreamHTLinkWidth:%hu \n" - " usMinUpStreamHTLinkWidth:%hu \n" - " usMinDownStreamHTLinkWidth:%hu \n", + " ulBootUpEngineClock:%lu\n" + " ulBootUpUMAClock:%lu\n" + " ulBootUpSidePortClock:%lu\n" + " ulMinSidePortClock:%lu\n" + " ulSystemConfig:%lu\n" + " ulBootUpReqDisplayVector:%lu\n" + " ulOtherDisplayMisc:%lu\n" + " ulDDISlot1Config:%lu\n" + " ulDDISlot2Config:%lu\n" + + " ucMemoryType:%u\n" + " ucUMAChannelNumber:%u\n" + " ucDockingPinBit:%u\n" + " ucDockingPinPolarity:%u\n" + + " ulDockingPinCFGInfo:%lu\n" + " ulCPUCapInfo: %lu\n" + + " usNumberOfCyclesInPeriod:%hu\n" + " usMaxNBVoltage:%hu\n" + " usMinNBVoltage:%hu\n" + " usBootUpNBVoltage:%hu\n" + + " ulHTLinkFreq:%lu\n" + + " usMinHTLinkWidth:%hu\n" + " usMaxHTLinkWidth:%hu\n" + " usUMASyncStartDelay:%hu\n" + " usUMADataReturnTime:%hu\n" + " usLinkStatusZeroTime:%hu\n" + + " ulHighVoltageHTLinkFreq:%lu\n" + " ulLowVoltageHTLinkFreq:%lu\n" + + " usMaxUpStreamHTLinkWidth:%hu\n" + " usMaxDownStreamHTLinkWidth:%hu\n" + " usMinUpStreamHTLinkWidth:%hu\n" + " usMinDownStreamHTLinkWidth:%hu\n", (unsigned long)vgainfo.ulBootUpEngineClock, (unsigned long)vgainfo.ulBootUpUMAClock, |