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authorKerry Sheh <shekairui@gmail.com>2011-09-14 10:04:19 +0800
committerPatrick Georgi <patrick@georgi-clan.de>2011-09-14 07:47:30 +0200
commit8c69b1d13b12a23d22de19b9de2e161e6064021c (patch)
treefdd2b4c452e0ea710d1bd456681af9834b503b40 /src/southbridge/amd/rs780/pcie.c
parenta25828dd0eaec09334ccbe05559d0e121e698b0d (diff)
rs780: hide unused gfx ports and gpp ports
Hide the unused gfx ports and gpp ports if they are not configured as hotplug. lspci -vvv will get more accurate information under Linux, tested on avalue/eax-785e. Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/rs780/pcie.c')
-rw-r--r--src/southbridge/amd/rs780/pcie.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 9cbd832661..5e2d985130 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -390,3 +390,16 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
switching_gpp_configurations(nb_dev, sb_dev);
ValidatePortEn(nb_dev);
}
+
+/**
+ * Hide unused Gpp port
+ */
+void pcie_hide_unused_ports(device_t nb_dev)
+{
+ u16 hide = 0x6FC; /* skip port 0, 1, 8 */
+
+ hide &= ~(AtiPcieCfg.PortDetect | AtiPcieCfg.PortHp);
+ printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide);
+ set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */
+ set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */
+}