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authorJoe Bao <zheng.bao@amd.com>2008-12-01 19:49:57 +0000
committerMarc Jones <marc.jones@amd.com>2008-12-01 19:49:57 +0000
commit40d46ba383de03ebb413ab0f3ac3af8301f5f813 (patch)
treec9bc261ccf0641b66e3692b933f8c347b4ee00f1 /src/southbridge/amd/rs690/rs690_ht.c
parent164463c551367d0ae3a9f8e5a1719200af99b060 (diff)
Add AMD rs690 VID DID reporting and some minor cleanups.
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs690/rs690_ht.c')
-rw-r--r--src/southbridge/amd/rs690/rs690_ht.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/rs690_ht.c b/src/southbridge/amd/rs690/rs690_ht.c
index 808a7225a5..40a85f6c17 100644
--- a/src/southbridge/amd/rs690/rs690_ht.c
+++ b/src/southbridge/amd/rs690/rs690_ht.c
@@ -61,7 +61,7 @@ static void pcie_init(struct device *dev)
dword |= (1 << 30); /* Clear possible errors */
pci_write_config32(dev, 0x04, dword);
- /*
+ /*
* 1 is APIC enable
* 18 is enable nb to accept A4 interrupt request from SB.
*/