diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-16 20:52:23 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-17 17:03:08 +0100 |
| commit | a9e3a756fe7a68c1839dd5a33b3aa03ca1224327 (patch) | |
| tree | bcac8ba7e7d415493b9fe6265518f7eee1da74d6 /src/southbridge/amd/rs690/pcie.c | |
| parent | 3c3a50c3c4144a393b4183d4e57ae9c7c2d8cc53 (diff) | |
southbridge/amd rs690 & rs780 spelling fixes
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/amd/rs690/pcie.c')
| -rw-r--r-- | src/southbridge/amd/rs690/pcie.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 0bd4da5735..d2817255e0 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -142,7 +142,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) reg |= cfg->gpp_configuration << 4; nbmisc_write_index(nb_dev, 0x67, reg); - /* read bit14 and write back its inverst value */ + /* read bit14 and write back its inverted value */ reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); reg ^= RECONFIG_GPPSB_GPPSB; nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); @@ -256,7 +256,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) case 7: /* Blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - /* Enabels TLP flushing */ + /* Enables TLP flushing */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* check port enable */ @@ -301,10 +301,10 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) } /* step 6b: L0s for the southbridge link */ - /* To enalbe L0s in the southbridage*/ + /* To enable L0s in the southbridge*/ /* step 6c: L0s for the GPP link(s) */ - /* To eable L0s in the RS690 for the GPP port(s) */ + /* To enable L0s in the RS690 for the GPP port(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8); reg16 = pci_read_config16(dev, 0x68); @@ -312,7 +312,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) pci_write_config16(dev, 0x68, reg16); /* step 6d: ASPM L1 for the southbridge link */ - /* To enalbe L1s in the southbridage*/ + /* To enable L1s in the southbridge*/ /* step 6e: ASPM L1 for GPP link(s) */; set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); |