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authorWANG Siyuan <wangsiyuanbuaa@gmail.com>2015-05-20 14:41:01 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-13 02:22:49 +0200
commitf2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 (patch)
tree3c0b66ab3395249ddfa4524ebc80bdf3007acc89 /src/southbridge/amd/pi/hudson/amd_pci_int_types.h
parent597ee56261c75c4e621a83e5999bc84e772ed53f (diff)
southbridge/amd/pi: Add support for new AMD southbridge Kern
Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/amd_pci_int_types.h')
-rw-r--r--src/southbridge/amd/pi/hudson/amd_pci_int_types.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index ad26d63633..b48f87e204 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
@@ -33,6 +33,10 @@ const char * intr_types[] = {
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+ [0x40] = "IDE\t", "SATA\t",
+ [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
+ [0x75] = NULL
#endif
};