From f2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 Mon Sep 17 00:00:00 2001 From: WANG Siyuan Date: Wed, 20 May 2015 14:41:01 +0800 Subject: southbridge/amd/pi: Add support for new AMD southbridge Kern Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan Signed-off-by: WANG Siyuan Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Stefan Reinauer --- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/southbridge/amd/pi/hudson/amd_pci_int_types.h') diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index ad26d63633..b48f87e204 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -33,6 +33,10 @@ const char * intr_types[] = { #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", + [0x75] = NULL #endif }; -- cgit v1.2.3