diff options
| author | Dave Frodin <dave.frodin@se-eng.com> | 2015-01-27 07:19:48 -0700 |
|---|---|---|
| committer | Dave Frodin <dave.frodin@se-eng.com> | 2015-02-05 17:33:00 +0100 |
| commit | 9cfa742a264442a8796120964b06fcc8e03185bf (patch) | |
| tree | 311dea3a9bd784725a4a68992c6428346e926949 /src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | |
| parent | c3f6bb086beeaca831877813589dc298faaa5dbe (diff) | |
southbridge/amd/pi: Add the bolton definitions
This adds the PCI and interrupt related definitions
for the bolton specific features.
Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/amd/pi/hudson/amd_pci_int_defs.h')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index e6bd2da4f5..78a40f0a91 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -25,7 +25,6 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_NC 0x1F /* Not Used */ #define PIRQ_A 0x00 /* INT A */ @@ -41,9 +40,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ @@ -67,6 +66,18 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define FCH_INT_TABLE_SIZE 0x54 +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif #endif /* AMD_PCI_INT_DEFS_H */ |