more warnings gone...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 17 insertions, 21 deletions

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 905d71f052..e974d399d1 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -35,7 +35,7 @@
 #include "cs5536.h"
 
 struct msrinit {
-	uint32_t msrnum;
+	u32 msrnum;
 	msr_t msr;
 };
 
@@ -61,8 +61,8 @@ struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
 };
 
 struct acpiinit {
-	uint16_t ioreg;
-	uint32_t regdata;
+	u16 ioreg;
+	u32 regdata;
 };
 
 struct acpiinit acpi_init_table[] = {
@@ -95,7 +95,7 @@ struct FLASH_DEVICE FlashInitTable[] = {
 
 #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
 
-uint32_t FlashPort[] = {
+u32 FlashPort[] = {
 	MDD_LBAR_FLSH0,
 	MDD_LBAR_FLSH1,
 	MDD_LBAR_FLSH2,
@@ -111,8 +111,8 @@ uint32_t FlashPort[] = {
 /* ***************************************************************************/
 static void pmChipsetInit(void)
 {
-	uint32_t val = 0;
-	uint16_t port;
+	u32 val = 0;
+	u16 port;
 
 	port = (PMS_IO_BASE + 0x010);
 	val = 0x0E00;		/*  1ms */
@@ -427,7 +427,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
 
 static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 {
-	uint8_t *bar;
+	u32 bar;
 	msr_t msr;
 	device_t dev;
 
@@ -443,7 +443,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		/* write to clear diag register */
 		wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
 
-		bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+		bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
 		/* Make HCCPARAMS writeable */
 		write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
@@ -455,7 +455,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
 			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
-		bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+		bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
 		write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
 
@@ -483,8 +483,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		dev = dev_find_device(PCI_VENDOR_ID_AMD, 
 				PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 		if (dev) {
-			bar = (uint8_t *) pci_read_config32(dev, 
-					PCI_BASE_ADDRESS_0);
+			bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			write32(bar + UDCDEVCTL,
 			       read32(bar + UDCDEVCTL) | UDC_SD_SET);
 
@@ -493,8 +492,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		dev = dev_find_device(PCI_VENDOR_ID_AMD,
 				PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 		if (dev) {
-			bar = (uint8_t *) pci_read_config32(dev,
-					PCI_BASE_ADDRESS_0);
+			bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
 			write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
 		}
@@ -524,7 +522,7 @@ void chipsetinit(void)
 {
 	device_t dev;
 	msr_t msr;
-	uint32_t msrnum;
+	u32 msrnum;
 	struct southbridge_amd_cs5536_config *sb =
 	    (struct southbridge_amd_cs5536_config *)dev->chip_info;
 	struct msrinit *csi;
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index fd09764212..8a553f57e0 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -32,13 +32,11 @@ static void cs5536_setup_extmsr(void)
 
 	/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
 	msr.hi = msr.lo = 0x00000000;
-	if (CS5536_GLINK_PORT_NUM <= 4) {
-		msr.lo = CS5536_DEV_NUM << 
-			(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
-	} else {
-		msr.hi = CS5536_DEV_NUM << 
-			(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
-	}
+#if CS5536_GLINK_PORT_NUM <= 4
+	msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
+#else
+	msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
+#endif
 	wrmsr(GLPCI_ExtMSR, msr);
 }