diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-18 19:18:56 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-20 17:15:32 +0200 |
| commit | c021ffee45f7b19b3a8e6c426e0d14a4609bf593 (patch) | |
| tree | 6c6a5667ccd217f5272f178271d360947eae1231 /src/southbridge/amd/cs5535 | |
| parent | bf7faa1a634e8bed0d0a8b6634dfe10f42ab986c (diff) | |
southbridge/amd: Add space around operators
Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16637
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/cs5535')
| -rw-r--r-- | src/southbridge/amd/cs5535/chipsetinit.c | 28 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5535/cs5535.c | 4 |
2 files changed, 16 insertions, 16 deletions
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index a6c0084087..1b7fe5dd80 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -22,11 +22,11 @@ struct msrinit { /* Master Configuration Register for Bus Masters. */ static struct msrinit SB_MASTER_CONF_TABLE[] = { - { USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, /* NOTE: Must be 1st entry in table */ - { USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, - { ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000} }, - { AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, - { MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000} }, + { USB1_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, /* NOTE: Must be 1st entry in table */ + { USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, + { ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000} }, + { AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, + { MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000} }, /* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLIU_SB_GLD_MSR_CONF, 0x0*/ @@ -35,15 +35,15 @@ static struct msrinit SB_MASTER_CONF_TABLE[] = { /* 5535_A3 Clock Gating*/ static struct msrinit CS5535_CLOCK_GATING_TABLE[] = { - { USB1_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { USB2_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, - { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { 0, {.hi=0, .lo=0x000000000} } + { USB1_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { USB2_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { GLIU_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x050554111} }, + { ATA_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { 0, {.hi = 0, .lo = 0x000000000} } }; #ifdef UNUSED_CODE diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 3f6e48ff55..2868683df7 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -56,9 +56,9 @@ static void dump_south(struct device *dev) { int i, j; - for (i=0; i<256; i+=16) { + for (i = 0; i < 256; i+=16) { printk(BIOS_DEBUG, "0x%02x: ", i); - for (j=0; j<16; j++) + for (j = 0; j < 16; j++) printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); printk(BIOS_DEBUG, "\n"); } |