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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 17:17:09 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:23 +0100 |
| commit | d5855ec5326f7696a22e0da776a63cc350c2dd16 (patch) | |
| tree | 626297818fb081a4024ad1c74830710b5b4bbf0f /src/southbridge/amd/common/amd_pci_util.c | |
| parent | 66208bd3d5203ccaf052c3e3663df702d367e4a7 (diff) | |
FSP1_1: Always use common code
Always use the common FSP code. Remove the FSP_RAM_INIT, FSP_ROMSTAGE,
FSP_STACK and FSP_STAGE_CACHE Kconfig values.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: Ib3d015cb2dc257e46c2340cc7bc09cf0ffb0492c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5197b1354d138759dfaa428c665de6cbfb8e8911
Original-Change-Id: I3e3c1c9e6f73009a099c1ec3688dbd8c326fc766
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306142
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12158
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/southbridge/amd/common/amd_pci_util.c')
0 files changed, 0 insertions, 0 deletions