diff options
| author | Dave Frodin <dave.frodin@se-eng.com> | 2014-06-05 14:30:22 -0600 |
|---|---|---|
| committer | Dave Frodin <dave.frodin@se-eng.com> | 2014-06-11 20:06:21 +0200 |
| commit | ac1b875b554f45b0c98d375369119495b7ad2a2a (patch) | |
| tree | cb397c9fe4972193e4b95808c37cfc267f160401 /src/southbridge/amd/cimx/sb900 | |
| parent | 61f902d4a7779d0ce30de79df7a71ad0c3788887 (diff) | |
amd/southbridge/lpc: SPI BAR has fixed size/location
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.
Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900')
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/lpc.c | 13 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/lpc.h | 5 |
2 files changed, 11 insertions, 7 deletions
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 5b414f41a5..ce1be11da7 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -31,8 +31,6 @@ void lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; @@ -46,6 +44,9 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Add a memory resource for the SPI BAR. */ + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); + res = new_resource(dev, 3); res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -60,11 +61,13 @@ void lpc_set_resources(struct device *dev) struct resource *res; printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n"); + + /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, 2); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); + pci_dev_set_resources(dev); - /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS); - pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index c0c5f20195..66f3ccd8cd 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h @@ -20,8 +20,9 @@ #ifndef _SB900_LPC_H_ #define _SB900_LPC_H_ - -#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define SPI_ROM_ENABLE 0x02 +#define SPI_BASE_ADDRESS 0xFEC10000 void lpc_read_resources(device_t dev); void lpc_set_resources(device_t dev); |