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authorJoe Moore <awokd@danwin1210.me>2019-10-21 01:03:08 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-11-20 13:23:01 +0000
commit2c08ea7cfcb24240e41ad0f75be35f9e2967b3d1 (patch)
tree533803d91d10448590e070353c5303483df2e6b3 /src/southbridge/amd/cimx/sb900/reset.c
parentdc0b1875a9196e593d9f25c4edbfd3b37c93e727 (diff)
cpu/nb/sb: Remove fam12
With removal of Torpedo mainboard, this code is no longer necessary. This also removes fam12 support from northbridge and SB900 from southbridge. Change-Id: I8a30461278844d0d9ad4320f0e952774c4fd644f Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900/reset.c')
-rw-r--r--src/southbridge/amd/cimx/sb900/reset.c48
1 files changed, 0 insertions, 48 deletions
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
deleted file mode 100644
index 787f7426ce..0000000000
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <device/pci_ops.h>
-#include <cf9_reset.h>
-#include <reset.h>
-
-#define HT_INIT_CONTROL 0x6C
-#define HTIC_BIOSR_Detect (1<<5)
-
-#define DEV_CDB 0x18
-#define NODE_PCI(x, fn) (((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn)))
-
-void cf9_reset_prepare(void)
-{
- u32 nodes;
- u32 htic;
- pci_devfn_t dev;
- int i;
-
- nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1;
- for (i = 0; i < nodes; i++) {
- dev = NODE_PCI(i, 0);
- htic = pci_read_config32(dev, HT_INIT_CONTROL);
- htic &= ~HTIC_BIOSR_Detect;
- pci_write_config32(dev, HT_INIT_CONTROL, htic);
- }
-}
-
-void do_board_reset(void)
-{
- system_reset();
-}