diff options
author | Joe Moore <awokd@danwin1210.me> | 2019-10-21 01:03:08 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:23:01 +0000 |
commit | 2c08ea7cfcb24240e41ad0f75be35f9e2967b3d1 (patch) | |
tree | 533803d91d10448590e070353c5303483df2e6b3 /src/southbridge/amd/cimx/sb900/lpc.c | |
parent | dc0b1875a9196e593d9f25c4edbfd3b37c93e727 (diff) |
cpu/nb/sb: Remove fam12
With removal of Torpedo mainboard, this code is no longer
necessary. This also removes fam12 support from northbridge
and SB900 from southbridge.
Change-Id: I8a30461278844d0d9ad4320f0e952774c4fd644f
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900/lpc.c')
-rw-r--r-- | src/southbridge/amd/cimx/sb900/lpc.c | 182 |
1 files changed, 0 insertions, 182 deletions
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c deleted file mode 100644 index 8e7c1cc67f..0000000000 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci.h> -#include <device/pci_ops.h> -#include "lpc.h" -#include <console/console.h> /* printk */ -#include <arch/ioapic.h> - - -void lpc_read_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - Start.\n"); - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); - - res = new_resource(dev, 3); - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - End.\n"); -} - -void lpc_set_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n"); - - /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, 2); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); - - pci_dev_set_resources(dev); - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n"); -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -void lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3]; - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); -/* - printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); -*/ - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); - break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - if (var_num >= 3) - continue; /* only 3 var ; compact them ? */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - break; - case 1: - reg_x |= (1 << 24); - break; - case 2: - reg_x |= (1 << 25); - break; - } - reg_var[var_num++] = - base & 0xffff; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 3: - pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ - case 2: - pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ - case 1: - //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata - break; - } - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - End.\n"); -} |