AGESA fam12 fam14 fam15: Use common agesa_readSpd()

Remove northbridge specific callouts for AGESA_READ_SPD.

Move low-level SMBus code to southbridge.

Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

3 files changed, 175 insertions, 1 deletions

diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 1c65eeeef9..95daf70d62 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -22,7 +22,7 @@
 
 romstage-y += cfg.c
 romstage-y += early.c
-romstage-y += smbus.c
+romstage-y += smbus.c smbus_spd.c
 romstage-y += reset.c
 
 ramstage-y += cfg.c
diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c
new file mode 100644
index 0000000000..e3f5acc95b
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci_def.h>
+#include <device/device.h>
+#include <stdlib.h>
+#include "OEM.h"		/* SMBUS0_BASE_ADDRESS */
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include "Porting.h"
+#include "AGESA.h"
+#include "chip.h"
+#include "smbus_spd.h"
+
+#include <northbridge/amd/agesa/dimmSpd.h>
+
+/* uncomment for source level debug - GDB gets really confused otherwise. */
+//#pragma optimize ("", off)
+
+/**
+ *	Read a single SPD byte.  If the first byte is being read, set up the
+ *	address and offset. Following bytes auto increment.
+ */
+static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
+						   int offset, int initial_offset)
+{
+	unsigned int status = -1;
+	UINT64 time_limit;
+
+	/* clear status register */
+	__outbyte(iobase + SMBUS_STATUS_REG, 0x1E);
+
+	if (offset == initial_offset) {
+		/* Clear slave status, set offset, set slave address and start reading */
+		__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x3E);
+		__outbyte(iobase + SMBUS_CONTROL_REG, offset);
+		__outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
+		__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
+	} else {
+		/* Issue read command - auto increments to next byte */
+		__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
+	}
+	/* time limit to avoid hanging for unexpected error status */
+	time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
+	while (__rdtsc() <= time_limit) {
+		status = __inbyte(iobase + SMBUS_STATUS_REG);
+		if ((status & SMBUS_INTERRUPT_MASK) == 0)
+			continue;	/* SMBusInterrupt not set, keep waiting */
+		if ((status & HOSTBUSY_MASK) != 0)
+			continue;	/* HostBusy set, keep waiting */
+		break;
+	}
+
+	if (status != STATUS__COMPLETED_SUCCESSFULLY)
+		return AGESA_ERROR;
+
+	buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
+	return AGESA_SUCCESS;
+}
+
+static void writePmReg(UINT8 reg, UINT8 data)
+{
+	__outbyte(PMIO_INDEX_REG, reg);
+	__outbyte(PMIO_DATA_REG, data);
+}
+
+static void setupFch(UINT16 ioBase)
+{
+	/* set up SMBUS - Set to SMBUS 0 & set base address */
+	/* For SB800 & Hudson1 to SB900 & Hudson 2/3 */
+	writePmReg(SMBUS_BAR_HIGH_BYTE, ioBase >> 8);
+	writePmReg(SMBUS_BAR_LOW_BYTE, (ioBase & 0xe0) | 1);
+
+	/* set SMBus clock to 400 KHz */
+	__outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
+}
+
+/**
+ *	Read one or more SPD bytes from a DIMM.
+ *	Start with offset zero and read sequentially.
+ *	Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
+					 UINT16 count)
+{
+	UINT16 index;
+	UINT8 status;
+	UINT8 initial_offset = 0;
+
+	setupFch(iobase);
+
+	for (index = initial_offset; index < count; index++) {
+		status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
+				initial_offset);
+		if (status != AGESA_SUCCESS)
+			return status;
+	}
+
+	return status;
+}
+
+int smbus_readSpd(int spdAddress, char *buf, size_t len)
+{
+	int ioBase = SMBUS0_BASE_ADDRESS;
+	setupFch (ioBase);
+	return readspd (ioBase, spdAddress, buf, len);
+}
diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.h b/src/southbridge/amd/cimx/sb800/smbus_spd.h
new file mode 100644
index 0000000000..30bf83f442
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/smbus_spd.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA
+ */
+
+#ifndef _SMBUS_SPD_H_
+#define _SMBUS_SPD_H_
+
+#define READ_BIT				0x01
+
+#define SMBUS_INTERRUPT_MASK	0x02
+#define HOSTBUSY_MASK			0x01
+
+#define SMBUS_READ_BYTE_COMMAND	0x48
+#define SMBUS_READ_COMMAND		0x44
+
+#define MAX_READ_TSC_COUNT		(2000000000 / 10)
+
+#define PMIO_INDEX_REG			0xCD6
+#define PMIO_DATA_REG			0xCD7
+
+#define SMBUS_BAR_LOW_BYTE		0x2C
+#define SMBUS_BAR_HIGH_BYTE		0x2D
+
+#define SMBUS_STATUS_REG		0x00
+#define SMBUS_SLAVE_STATUS_REG	0x01
+#define SMBUS_COMMAND_REG		0x02
+#define SMBUS_CONTROL_REG		0x03
+#define SMBUS_HOST_CMD_REG		0x04
+#define SMBUS_DATA0_REG			0x05
+#define SMBUS_CLOCK_REG			0x0E
+
+#define STATUS__COMPLETED_SUCCESSFULLY	0x02
+
+#define SMBUS_FREQUENCY_CONST	66000000 / 4
+
+#endif