diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 17:41:23 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-05 17:01:48 +0000 |
| commit | 287ce5f1ee8c3765d05bfbc0a6dd5ea9ec8b5c87 (patch) | |
| tree | 9ffb1915bf2186e3a5f41af09f968d5b3ce1902a /src/southbridge/amd/cimx/sb800 | |
| parent | d913036e18034d6756805aabd868e1091c97ac0c (diff) | |
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/early.c | 7 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 6 |
3 files changed, 8 insertions, 10 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 5decebfac4..6e0b54434c 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -83,7 +83,6 @@ static void enable_spi_fast_mode(void) static void enable_clocks(void) { u32 reg32; - volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40); // Program SB800 MiscClkCntrl register to configure clock output on the // 14M_25M_48M_OSC ball usually used for the Super-I/O. @@ -91,12 +90,12 @@ static void enable_clocks(void) // which is the SB800's power up default. We could switch back to 14 // in the mainboard's romstage.c, but then the clock frequency would // change twice. - reg32 = *acpi_mmio; + reg32 = misc_read32(0x40); reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) #if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK) reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz #endif - *acpi_mmio = reg32; + misc_write32(0x40, reg32); } void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 48829578e1..2ee4d40230 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <amdblocks/acpimmio.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ @@ -41,9 +42,7 @@ void sb_Poweron_Init(void) */ void sb800_clk_output_48Mhz(void) { - /* AcpiMMioDecodeEn */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0); - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ + misc_write32(0x40, misc_read32(0x40) & (~5)); + misc_write32(0x40, misc_read32(0x40) | 2); } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 4233a6ff0d..d6003bede2 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ - +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> /* device_operations */ @@ -400,9 +400,9 @@ static void sb800_enable(struct device *dev) * to function as GPIO {GPIO 35:0}. */ if (!sb_chip->disconnect_pcib && dev->enabled) - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); + pm_write8(0xea, pm_read8(0xea) & 0xfe); else - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0); + pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1); break; case PCI_DEVFN(0x14, 6): /* 0:14:6 GEC */ |