diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-18 01:17:38 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-30 05:17:16 +0200 |
| commit | 12bce3ff93334c14f388eea606a530737c5d9d21 (patch) | |
| tree | 094d67872bf8f6959e349d34d9d9c38742dfa654 /src/southbridge/amd/cimx/sb800/late.c | |
| parent | 221761e0be8fbf5ae5cae827216ae0e92c05c3af (diff) | |
SB800: Port to 64bit
Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10582
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/late.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ada673a89..cf7fb1cc0c 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -92,7 +92,8 @@ static u32 sb800_callout_entry(u32 func, u32 data, void* config) static void ahci_raid_init(struct device *dev) { u8 irq = 0; - u32 bar5, caps, ports, val; + void *bar5; + u32 caps, ports, val; val = pci_read_config16(dev, PCI_CLASS_DEVICE); if (val == PCI_CLASS_STORAGE_SATA) { @@ -105,18 +106,18 @@ static void ahci_raid_init(struct device *dev) } irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); - bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); + bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq); - caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = read32(bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + ports= read32(bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); + val = read32(bar5 + HOST_CTL); if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN); } dev->command |= PCI_COMMAND_MASTER; |