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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-04-15 20:07:53 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-05-18 06:48:57 +0200
commit61be3603f4b9f353e605d7b7c8d0d9f3b90f5636 (patch)
tree0de776853b482a83faff1ca5bbfdc2df243f7214 /src/southbridge/amd/cimx/sb700/Makefile.inc
parent17bb225be7dd031b9803f33dec88e9d53e3a582f (diff)
AGESA: Fix UMA calculations
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb700/Makefile.inc')
-rw-r--r--src/southbridge/amd/cimx/sb700/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc
index ab668e2024..0b9ee9ce33 100644
--- a/src/southbridge/amd/cimx/sb700/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb700/Makefile.inc
@@ -19,9 +19,11 @@
romstage-y += early.c
romstage-y += smbus.c smbus_spd.c
romstage-y += reset.c
+romstage-y += ramtop.c
ramstage-y += late.c
ramstage-y += reset.c
+ramstage-y += ramtop.c
ramstage-y += smbus.c
ramstage-y += lpc.c