From 61be3603f4b9f353e605d7b7c8d0d9f3b90f5636 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 15 Apr 2017 20:07:53 +0300 Subject: AGESA: Fix UMA calculations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/19328 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Marshall Dawson --- src/southbridge/amd/cimx/sb700/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/southbridge/amd/cimx/sb700/Makefile.inc') diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc index ab668e2024..0b9ee9ce33 100644 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -19,9 +19,11 @@ romstage-y += early.c romstage-y += smbus.c smbus_spd.c romstage-y += reset.c +romstage-y += ramtop.c ramstage-y += late.c ramstage-y += reset.c +ramstage-y += ramtop.c ramstage-y += smbus.c ramstage-y += lpc.c -- cgit v1.2.3