Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 42 insertions, 42 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index 1390065c09..2707ca6b43 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -13,8 +13,8 @@ void amd8111_enable(device_t dev)
 
 	/* See if we are on the bus behind the amd8111 pci bridge */
 	bus_dev = dev->bus->dev;
-	if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && 
-	    (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) 
+	if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
+	    (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
 	{
 		unsigned devfn;
 		devfn = bus_dev->path.pci.devfn + (1 << 3);
@@ -33,7 +33,7 @@ void amd8111_enable(device_t dev)
 		return;
 	}
 	if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
-	    (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) 
+	    (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA))
 	{
 		uint32_t id;
 		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
@@ -66,7 +66,7 @@ void amd8111_enable(device_t dev)
 
 struct chip_operations southbridge_amd_amd8111_ops = {
 	CHIP_NAME("AMD-8111 Southbridge")
-	/* This only called when this device is listed in the 
+	/* This only called when this device is listed in the
 	* static device tree.
 	*/
 	.enable_dev = amd8111_enable,
diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/amd8111_ac97.c
index 697915e002..f49c9bfd5f 100644
--- a/src/southbridge/amd/amd8111/amd8111_ac97.c
+++ b/src/southbridge/amd/amd8111/amd8111_ac97.c
@@ -10,7 +10,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x2c, 
+	pci_write_config32(dev, 0x2c,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c
index 32e3808a98..2ad54b78f6 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/amd8111_acpi.c
@@ -28,7 +28,7 @@ static int lsmbus_recv_byte(device_t dev)
 
 	device = dev->path.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-	
+
 	return do_smbus_recv_byte(res->base, device);
 }
 
@@ -51,7 +51,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
 
 	device = dev->path.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-	
+
 	return do_smbus_read_byte(res->base, device, address);
 }
 
@@ -62,7 +62,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 
 	device = dev->path.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-	
+
 	return do_smbus_write_byte(res->base, device, address, val);
 }
 
@@ -109,7 +109,7 @@ static void acpi_init(struct device *dev)
 	 */
 	byte = pci_read_config8(dev, 0x41);
 	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
-	
+
 	/* power on after power fail */
 	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
@@ -126,7 +126,7 @@ static void acpi_init(struct device *dev)
 	 */
 	byte = pci_read_config8(dev, 0x4a);
 	pci_write_config8(dev, 0x4a, byte | (1<<6));
-	
+
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
@@ -177,12 +177,12 @@ static void acpi_enable_resources(device_t dev)
 
 	/* Set the class code */
 	pci_write_config32(dev, 0x60, 0x06800000);
-	
+
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x7c, 
+	pci_write_config32(dev, 0x7c,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -204,7 +204,7 @@ static struct device_operations acpi_ops  = {
 	.init             = acpi_init,
 	.scan_bus         = scan_static_bus,
 	/*  We don't need amd8111_enable, chip ops takes care of it.
-	 *  It could be useful if these devices were not 
+	 *  It could be useful if these devices were not
 	 *  enabled by default.
 	 */
 //	.enable           = amd8111_enable,
diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c
index 3b6f5a0a65..3299875187 100644
--- a/src/southbridge/amd/amd8111/amd8111_ide.c
+++ b/src/southbridge/amd/amd8111/amd8111_ide.c
@@ -42,7 +42,7 @@ static void ide_init(struct device *dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 85e217bb65..8fe4982721 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -19,11 +19,11 @@
 static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
-	
+
 	pci_write_config32(dev,0xa0, 0xfed00001);
 	hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
 	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
-	
+
 }
 
 static void lpc_init(struct device *dev)
@@ -40,7 +40,7 @@ static void lpc_init(struct device *dev)
 
 	/* posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0)); 
+	pci_write_config8(dev, 0x46, byte | (1<<0));
 
 	/* Enable 5Mib Rom window */
 	byte = pci_read_config8(dev, 0x43);
@@ -65,11 +65,11 @@ static void lpc_init(struct device *dev)
 	pci_write_config8(dev, 0x40, byte);
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
-	if (nmi_option) {			
+	if (nmi_option) {
 		byte |= (1 << 7); /* set NMI */
 		pci_write_config8(dev, 0x40, byte);
 	}
-	
+
 	/* Initialize the real time clock */
 	rtc_init(0);
 
@@ -114,7 +114,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c
index 8818b51b40..4ab7212eda 100644
--- a/src/southbridge/amd/amd8111/amd8111_nic.c
+++ b/src/southbridge/amd/amd8111/amd8111_nic.c
@@ -25,20 +25,20 @@ typedef enum {
 	ASF_INIT_DONE_ALIAS	= (1 << 29),
 	/* VAL2 */
 	JUMBO			= (1 << 21),
-	VSIZE			= (1 << 20),	
+	VSIZE			= (1 << 20),
 	VLONLY			= (1 << 19),
-	VL_TAG_DEL		= (1 << 18),	
+	VL_TAG_DEL		= (1 << 18),
 	/* VAL1 */
-	EN_PMGR			= (1 << 14),			
+	EN_PMGR			= (1 << 14),
 	INTLEVEL		= (1 << 13),
-	FORCE_FULL_DUPLEX	= (1 << 12),	
-	FORCE_LINK_STATUS	= (1 << 11),	
-	APEP			= (1 << 10),	
-	MPPLBA			= (1 << 9),	
+	FORCE_FULL_DUPLEX	= (1 << 12),
+	FORCE_LINK_STATUS	= (1 << 11),
+	APEP			= (1 << 10),
+	MPPLBA			= (1 << 9),
 	/* VAL0 */
-	RESET_PHY_PULSE		= (1 << 2),	
-	RESET_PHY		= (1 << 1),	
-	PHY_RST_POL		= (1 << 0),	
+	RESET_PHY_PULSE		= (1 << 2),
+	RESET_PHY		= (1 << 1),
+	PHY_RST_POL		= (1 << 0),
 }CMD3_BITS;
 
 static void nic_init(struct device *dev)
@@ -72,7 +72,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
-	
+
 static struct device_operations nic_ops  = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index 9b26bcb90d..c96e898aea 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -67,7 +67,7 @@ void hard_reset(void)
 	 */
 	bus = node_link_to_bus(node, link);
 	dev = pci_locate_device_on_bus(
-		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), 
+		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
 		bus);
 
 	/* Reset */
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.c b/src/southbridge/amd/amd8111/amd8111_smbus.c
index 2554fd0c5e..0a0c58dce3 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.c
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.c
@@ -13,7 +13,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x44, 
+	pci_write_config32(dev, 0x44,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index b5799666e9..fe9b3bff8c 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -27,7 +27,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 			break;
 		}
 		if(loops == (SMBUS_TIMEOUT / 2)) {
-			outw(inw(smbus_io_base + SMBGSTATUS), 
+			outw(inw(smbus_io_base + SMBGSTATUS),
 				smbus_io_base + SMBGSTATUS);
 		}
 	} while(--loops);
@@ -41,7 +41,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	do {
 		unsigned short val;
 		smbus_delay();
-		
+
 		val = inw(smbus_io_base + SMBGSTATUS);
 		if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
 			break;
@@ -58,7 +58,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@@ -103,7 +103,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@@ -146,7 +146,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c
index f1c331dbaf..13dccf435b 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb.c
@@ -12,7 +12,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c
index 3aa5211dd0..89115c3bbe 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb2.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb2.c
@@ -11,7 +11,7 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x70, 
+	pci_write_config32(dev, 0x70,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -23,7 +23,7 @@ static struct pci_operations lops_pci = {
 
 static void amd8111_usb2_enable(device_t dev)
 {
-	// Due to buggy USB2 we force it to disable. 
+	// Due to buggy USB2 we force it to disable.
 	dev->enabled = 0;
 	amd8111_enable(dev);
 	printk(BIOS_DEBUG, "USB2 disabled.\n");
diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h
index 6c97ef2232..601038c441 100644
--- a/src/southbridge/amd/amd8111/chip.h
+++ b/src/southbridge/amd/amd8111/chip.h
@@ -1,7 +1,7 @@
 #ifndef AMD8111_CHIP_H
 #define AMD8111_CHIP_H
 
-struct southbridge_amd_amd8111_config 
+struct southbridge_amd_amd8111_config
 {
 	unsigned int ide0_enable : 1;
 	unsigned int ide1_enable : 1;